Release Notes

*** New Features

• Added built-in tests.
• register_alias - write one register, read all
• power_on_reset - read all registers, check against reset value
• walking_zeros - write walking zeros, read back, compare
• walking_ones - write walking ones, read back, compare
• write_read - do a write then a read
• Ported to NCSim.

Certain SystemVerilog features and capabilities are re-implemented for NCSIM.  Those changes are wrapped with `ifdef NCV.  You can run Questa with those turned on if you like: vlog +define+NCV ...

Due to the port to NCSim, any function that returned a list had to be changed to return the list as an output argument to the function.  For example, peek_bytes() changed from

function bytearray_t peek_bytes( address_t address, int nbytes);

to function void peek_bytes( output bytearray_t ba, address_t address, int nbytes);

Another example is get_register_array(), which changed from

virtual function register_list_t get_register_array();

to virtual function void get_register_array( output register_list_t register_array);

• Added UNPREDICTABLEMASK.
• Added compare_read_only_bits for selective inclusion or exlusion of read-only bits in the compare.
• Added mapped_register_container (replaces uvm_register_map_base) You can now add a register file to another register file (in addition to all previous behavior)
• ’resetvalue’ in register constructor is now deprecated.
• Note: uvm_register 2.0 changes the inheritance hierarchy of the registers.  This causes a backward compatibility issue.  In your register definition files (regdef.sv), you need to change the uvm_component “parent” to uvm_named_object:

function new(string name, uvm_component parent); ... endfunction

should change to function new(string name, uvm_named_object parent); ... endfunction

Furthermore, a register used to be an uvm_transaction.  Now it is an ‘uvm_named_object’ - it has hierarchy, and a parent, but it doesn’t have phasing and other uvm_component attributes.

Register maps and register files are also uvm_named_objects.

The main reason to change to uvm_named_objects was to make it much easier to copy and clone registers and register maps.

Bug Fixes

• Enhanced bus_read_bv() error message.
• Set a register initial values to its reset value automatically.

New files

uvm_broadcast_register.svh uvm_indirect_register.svh

Updated examples 11_masking_notification

New examples

14_register_map_lookup 15_backdoor 16_apb_zin 17_broadcast_registers 18_ap_notification 19_constraints 20_simple_indirect

Adds support for

• Hierarchical address maps
• Register alias names
• Add a register file into a register file.

Compatibility Issues

New Register Inheritance In register definitions, the register parent used to be ‘uvm_component’.  It is now ‘uvm_named_object’.  You must change the register construction definition:

Old

< function new(string name, uvm_component p); New:

function new(string name, uvm_named_object p);

Lightweight analysis ports

Constructor arguments.  Creating registers using the factory.

reset() uses poke() now instead of write().

ReadOnly bits can be updated by the shadow

Versions supported

• Tested on Questa 6.4[a,b,c,d,e] and 6.5[a,b].
• Tested on Windows and Linux.
• Tested with UVM 2.0, UVM 2.0.1 and UVM 2.0.2.

Changes in 2.0 beta 2

bus_read_bv() message changed to be more informative.

Formalizes the existing, field tested final beta8.

Release: January 25, 2010

Versions supported

• Tested on Questa 6.4f, 6.5{a,b,c,d} and 6.6.
• Tested on Windows and Linux.
• Tested with UVM 2.0.1, 2.0.3 and UVM 2.1.

New files

• src/uvm_coherent_register.svh
• src/uvm_fifo_register.svh
• src/uvm_memory.svh
• src/uvm_register_macros.svh

Adds support for

• coherent registers
• fifo registers
• semaphore locking
• simple memory interface
• field access “by name”

Extends support for various field and register permissions and usages.  For example a field can now have “RW” permission when accessed from one bus, and “RO” permission when accessed from another bus.

• Added support for simple memory api (See 09_memory_simple).
• Added support for coherent registers (See 10_coherent_registers).
• Added support for more access policies and for register permissions based on address.  (11_masking_notification)
• Added support for fifo registers (12_fifo_registers).
• Added support for “by name” access to fields (13_field_by_name).
• NO API changes which break backward compatibility.

Versions supported

• Tested on Questa 6.4a, 6.4b, 6.4c and 6.5.
• Tested on Windows and Linux.
• Tested with UVM 2.0 and UVM 2.0.1.

New in 1.0 Beta 8

• Coherent register types
• FIFO register types
• Simple Semaphore locking on registers
• Field Access By Name
• Simple Memory API.  Memory functionality will be expanded in a future release with backward compatible API.
• Assigning register access policy based on address.  Adds support for registers which have one kind of permission when they are accessed via bus 1, and another kind of permission when they are accessed via bus 2.  For example, regA is RW on the AHB bus, but RO on the I2C bus.

Changes in 1.0 beta 8

• Enhanced field and register access policies.  The complete list is now RW, RO, WO, Clear-on-Read, Set-on-Read, Write-Zero-to-Set and Write-One-to-Clear.

Adds support for backdoor access, an id register implementation and a modal register implementation.

• Added support for library backdoor access and test (05_backdoor_simple).
• Added example ‘id_register’ implementation and test (06_id_registers).
• Added a modal register implementation and test (08_register_field_modes)
• Normalized some API function names.
• NO API changes.
• Tested on Questa 6.4a, 6.4b, 6.4c and 6.5.
• Tested on Windows and Linux.
• Tested with UVM 2.0 and UVM 2.0.1.

New in 1.0 Beta 7

• Added backdoor access support via a C implementation.  If you want to use backdoor access, then you must compile the DPI C code.  (Pre-compiled libraries for linux, linux_x86_64 and cygwin are shipped with the library) (There is a makefile provided, but you may need to modify to suit).

vlog +incdir+$(UVM_HOME)/src+$(UVM_REGISTER_HOME)/src \
  +define+BACKDOOR_DPI \
  $(UVM_REGISTER_HOME)/src/uvm_register_pkg.sv

• Added new examples

05_backdoor_simple

05_backdoor_simple is a simple example of using the shadow register to write directly to an HDL path name.  (via the PLI - a backdoor into the design).

06_id_register

06_id_register is an example of a special functionality in a register - an ID register.  This ID register is not a general purpose register, but is provided to use as is or as a demonstration of how to create your own special purpose register functionality.  See uvm_id_register.svh

08_register_field_modes

08_register_field_modes is an example of a special functionality in a register - a modal register.  This modal register is a register whose field representation changes depending on which mode it is in.  It is provided as a demonstration of using modes.  It is expected that most modal registers are customer specific, and so this modal register and example serves as a template for customization.

Changes in 1.0 beta 7

• Changed uvm_register-1.0beta7/src/uvm_register.svh

Added backdoor access support.

Normalized names.  Raw access is peek_*() or poke_*().  Masked access is read_data32() or write_data32() (set_data32() still exists but is deprecated in favor of peek_data32())

Added get_byte_array_no_masking().

Cleaned up error messaging.

• Added uvm_register-1.0beta7/src/uvm_register_dpi.c and uvm_register-1.0beta7/src/uvm_register_dpi.svh

Backdoor implementation.

• Changed uvm_register-1.0beta7/src/uvm_register_env_pkg.svh

Message printing fixed.

Added additional examples.  Instrumented library with MACROS.  NO API changes.

• Tested on Questa 6.4a, 6.4b, 6.4c and 6.5 Beta.
• Tested on Windows and Linux.
• Tested with UVM 2.0 and UVM 2.0.1.

New in 1.0 Beta 6

Added new examples 02_register_transactions 03_layered_sequences 04_simple_bus

01_bus_transactions contains new sequences and interesting constraints.  All register fields can be random in this example.

02_register_transactions is simple example that builds a driver and a sequencer for register transactions.  Register sequence is started, and the register driver prints them.

03_layered_register_sequences is a simple example that builds a layer of register transactions over bus transactions.  The register transactions generated from the automatic test are converted into bus specific transactions.

04_simple_bus is a simple example that shows a bus with an OVC-style component integrated to a register test.

Changes in 1.0 beta 6

Library components changes

Added factory registration for all library components.  Added field automation.

• Changed auto test default sequence name from register_sequence_all_registers_REQ_RSP to register_sequence_all_registers#(REQ, RSP)
• uvm_register.svh: Removed ‘class uvm_register_monitor’ (not used)
• uvm_register_agent_pkg.svh: Changed the name of uvm_register_scoreboard to uvm_register_monitor.
• uvm_register_env_pkg.svh: Instantiated a register_bus_monitor to publish register transactions to the built in scoreboard.

Copyrights adjusted from 2008 to 2009.  Changed base type of uvm_register_bus_driver from uvm_threaded_component to uvm_component.  Changed base type of uvm_register_auto_test from uvm_threaded_component to uvm_component.

General housecleaning.  Added NaturalDocs automated documentation generation.

• Tested on Questa 6.4, 6.4a, 6.4b, 6.4c and 6.5 Beta 1.
• Tested on Windows and Linux.
• Tested with UVM 2.0 and UVM 2.0.1.

Package name changed to ‘uvm_register_pkg’.  Use it as import uvm_register_pkg::*;

Added Natural Docs comments to allow HTML documentation generation.

Future development plans (suggestions/priority welcome)

1) Example register verification on an XBUS OVC.  2) Backdoor access.  3) Auto-generation of SystemVerilog register definitions from a standard format.  4) Memory support.