Variable Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
A
 address
bus_transaction
C
 channel
uvm_register_auto_testuvm_register_bus_driver
 compare_read_only_bits
uvm_register
 compareMask
uvm_register
D
 data
bus_transactionuvm_registeruvm_register_transaction
E
 end_address
uvm_memory
M
 m_bus_driver
uvm_register_env
 m_driver
uvm_register_env
 m_register_map
uvm_register_env
 m_register_monitor
uvm_register_env
 m_sequencer
uvm_register_env
 mem[int]
uvm_memory
N
 name
uvm_register_transaction
O
 op
bus_transactionuvm_register_transaction
 UVM_REGISTER_MAX_WIDTH
P
 previous_data
uvm_register
R
 ranges
uvm_memory
 register_attribute
uvm_register_base
 register_map
uvm_register_bus_driveruvm_register_bus_monitoruvm_register_monitoruvm_register_sequencer
 register_name
uvm_register_base
 register_type
uvm_register_base
 resetValue
uvm_register
 RMASK
uvm_register
S
 slaves[$]
uvm_coherent_register_master
 start_address
uvm_memory
 status
bus_response
U
 UNPREDICTABLE
uvm_register
W
 WMASK
uvm_register
rand addressWidth_t address
Address of this transaction
uvm_tlm_transport_channel #(REQ,
RSP) channel
The communication channel contained in this class.
uvm_tlm_transport_channel #(REQ,
RSP) channel
The channel is used to
bit compare_read_only_bits = 0
If set, then READ-ONLY bits are included in compare operations.
T compareMask = '1
This bit mask is used to define bits that should not participate in a comparison.
rand dataWidth_t data
Data for the transaction
rand T data
The register data.
rand dataWidth_t data
Data for the transaction
address_t end_address
The last legal address to use in this memory.
uvm_register_bus_driver #(uvm_register_transaction,
uvm_register_transaction) m_bus_driver
The bus_driver contained in the env.
uvm_register_driver #(uvm_register_transaction,
uvm_register_transaction) m_driver
The driver contained in the env.
uvm_register_map m_register_map
Convenient place to house the register map for users of this env to reference.
uvm_register_monitor #(uvm_register_transaction) m_register_monitor
The register monitor contained in the env.
uvm_register_sequencer #(uvm_register_transaction,
uvm_register_transaction) m_sequencer
The sequencer contained in the env.
T mem[int]
A “regular” verilog memory implemented as an associative array (sparse array).
string name
Name for the register
rand op_code_t op
rand op_code_t op
parameter int UVM_REGISTER_MAX_WIDTH = `UVM_REGISTER_MAX_WIDTH
This parameter will be looked up by the DPI-C code using: vpi_handle_by_name( “uvm_register_pkg::UVM_REGISTER_MAX_WIDTH”, 0);
T previous_data
The previous value of the register.
uvm_memory_ranges ranges
This is the list of managed (and unmanaged) addresses.
string register_attribute
Optional field.
uvm_register_map register_map
The register map that will be used for address lookup.
uvm_register_map register_map
The register map that lookups will occur in.
uvm_register_map register_map
The register map that will be used for name lookup.
uvm_register_map register_map
Can be used by sequences to find out what registers are available.
protected string register_name
The name of the register; a simple string usually.
string register_type
The type of the register; an optional field.
T resetValue
The reset value.
T RMASK = '1
This bit mask defines bits that are readable.
uvm_coherent_register_slave #(T) slaves[$]
The list of all the slaves “managed”.
address_t start_address
The first legal address to use in this memory.
status_t status
Response status.
T UNPREDICTABLEMASK = '0
This bit mask is used as an additional compare mask.
T WMASK = '1
This bit mask defines bits that are writable.